Dynamic Random Access Memory (DRAM) integrated circuit arrays have been existence for several years, with their dramatic increase in storage capacity having been achieved through advances in semiconductor fabrication technology and circuit design technology. The considerable advances in these two technologies have also resulted in higher and higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
A DRAM memory cell typically includes, as basic components, an access transistor (switch) and a capacitor for storing a binary data bit in the form of a charge. Typically, a first voltage is stored on the capacitor to represent a logic HIGH or binary “1” value (e.g., VDD), while a second voltage on the storage capacitor represents a logic LOW or binary “0” value (e.g., ground). A basic drawback of a DRAM device is that the charge on the capacitor eventually leaks away and therefore provisions must be made to “refresh” the capacitor charge, otherwise the data bit stored by the memory cell is lost.
The memory cell of a conventional Static Random Access Memory (SRAM), on the other hand, includes, as basic components, an access transistor or transistors and a memory element in the form of two or more integrated circuit devices interconnected to function as a bistable latch. An example of such a bistable latch is a pair of cross-coupled inverters. Bistable latches do not need to be “refreshed,” as in the case of DRAM memory cells, and will reliably store a data bit indefinitely so long as they continue to receive supply voltage. However, such a memory cell requires a larger number of transistors and therefore a larger amount of silicon real estate than a simple DRAM cell, and draws more power than a DRAM cell Like a DRAM array, an SRAM array is also a form of volatile memory in that the data is lost once power is removed.
Phase Change Random Access Memory (“PCRAM” also referred to as “PRAM” and generally as phase change memory “PCM”) is an emerging non-volatile memory technology which stores data using phase change materials (such as Ge—Sb—Te (GST) alloys) having a programmable electrical resistance that changes with temperature. Other compositions such as GeSb4, (including substitution/addition of other elements) are also possible for the phase change materials. Individual phase change elements (PCE) are thus used as the storage cells of a memory device. The state of an individual PCE is programmed through a heating and cooling process which is electrically controlled by passing a current through the PCE (or a discrete heating element in proximity to the PCE) and the resulting ohmic heating that occurs. Depending upon the specific applied temperature and duration of heating applied to the PCE element, the structure is either “set” to a lower resistance crystalline state or “reset” to an amorphous, higher resistance state.
The changing of the phase of a PCE typically requires a high temperature (e.g., above 200° C. to 900° C. depending on material properties), as can be obtained by Joule heating from current flowing through the phase change material or discrete resistor. When the phase change material is heated above its melting temperature to thereafter be quickly cooled, the phase change material becomes amorphous to store a data bit of “1.” Alternatively, when the phase change material is heated above its crystallization temperature and maintained at that temperature for a predetermined time before cooling, the phase change material becomes crystalline to store a data bit of “0.”
In an exemplary thermal cycling operation of a phase change material used as a PCE storage cell a first thermal cycling operation includes a “RESET” pulse for converting the PCE from crystalline to amorphous form, and a second thermal cycling operation includes a “SET” pulse for converting the PCE from amorphous to crystalline form. During the RESET pulse, the temperature of the PCM is raised above its melting temperature (Tm), followed by a rapid quench over a short time t1. As a result of the rapid quench, the disordered arrangement of atoms of the PCM due to the melt is retained. Thus, the PCM is left in an amorphous, high resistive state after the RESET pulse. During the SET pulse, the PCM is annealed at a lower temperature with respect to the melting temperature, and for a longer time t2 with respect to t1. This process enables the amorphous form to crystallize into a lower resistive state.
An aspect to the feasibility of PCE memory technology is the ability to design large-scale arrays so as to allow random access of millions of bits. This may be done, for example through an array of PCEs, each gated by associated access transistors using a matrix of word lines (WL) (e.g., formed from a polysilicon gate material) and bit lines (BL) (e.g., formed with metal interconnect material). The current passing through the PCE may be controlled via the bit line (BL) and/or word line (WL).
The material of the PCE requires a certain amount of time to “settle out” to a thermal and crystal equilibrium state after a write operation is performed, due to the fact that the material of the PCE is undergoing a structural change during the write operation. The time to settle out may, in some circumstances, be longer than the cycle time of the chip that is writing to and reading from the memory. For example, it might take 30 ns for a PCE to settle out after a write operation, whereas the cycle time of the chip may be 10 ns. This can lead to an undesired situation in which the chip attempts to read or write to the PCE before the PCE is ready for the next operation.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.